Methods and apparatus for forming a polysilicon capacitor

ABSTRACT

An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.

FIELD

This invention relates generally to polysilicon capacitors, moreparticularly to methods and apparatus for forming a polysiliconcapacitor with a low voltage capacitance coefficient.

DESCRIPTION OF THE RELATED ART

Polysilicon-to-polysilicon capacitors (“polysilicon capacitors”) are agenerally well known device. U.S. Pat. No. 5,037,772, commonly assignedand hereby incorporated by reference in its entirety, describes a methodfor forming a polysilicon capacitor.

Polysilicon capacitors are useful in circuit design and manufacture. Theuse of polysilicon capacitors can be often desirable as a front endprocess because of the higher quality materials that are used andobviate a need for a second mask as with conventional back-endprocesses.

However, polysilicon capacitors can become problematic in linearcircuits. Linear circuit applications require capacitors to have a flatand low voltage capacitance coefficient (“VCC”) over a voltage range.Current polysilicon capacitors can not match the performancecharacteristics of metal capacitors or polysilicon-to-metal capacitors.One limitation to the performance of polysilicon capacitors is thatconventional polysilicon capacitors show greater dispersion over thevoltage range because of depletion of the electrodes. In contrast, metalcapacitors dispersion is a result of nitride defects. Accordingly, whatis needed in the art is a polysilicon-to-polysilicon capacitor withcomparable or better performance characteristics than metal capacitorsfor linear operations.

SUMMARY

An embodiment relates generally to a method of forming a capacitor. Themethod includes depositing a first layer of polysilicon on a substrateand implanting a high dose of implant into the first layer ofpolysilicon. The method also includes depositing a layer of dielectricover the first layer of polysilicon and depositing a second layer ofpolysilicon over the layer of dielectric. The method further includesimplanting an equivalent concentration of implant species into the firstand second layer of polysilicon.

Another embodiment pertains generally to a capacitor. The capacitorincludes a first layer of polysilicon deposited over a substrate and adielectric layer deposited over the first layer of polysilicon. Thecapacitor also includes a second layer of polysilicon deposited over thedielectric layer, where the first layer of polysilicon and the secondlayer of polysilicon are implanted with dopant in substantiallyequivalent concentrations.

Yet another embodiment relates generally to a method for forming anintegrated circuit in and on a silicon substrate with a polysiliconcapacitor. The method includes depositing a first layer of polysiliconon a substrate and implanting a high dose of implant into the firstlayer of polysilicon. The method also includes depositing a layer ofdielectric over the first layer of polysilicon and depositing a secondlayer of polysilicon over the layer of dielectric. The method furtherincludes implanting an equivalent concentration of implant as the firstlayer of polysilicon into the second layer of polysilicon.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features of the embodiments can be more fully appreciated, asthe same become better understood with reference to the followingdetailed description of the embodiments when considered in connectionwith the accompanying figures, in which:

FIGS. 1A-1E collectively depict a process for forming an embodiment ofthe present teachings;

FIG. 2 depicts a graph comparing voltage linearity of metal capacitorsand embodiments of the present teachings; and

FIG. 3AB collectively depict the voltage linearity of an embodiment ofthe present teachings.

DETAILED DESCRIPTION OF EMBODIMENTS

For simplicity and illustrative purposes, the principles of the presentinvention are described by referring mainly to exemplary embodimentsthereof. However, one of ordinary skill in the art would readilyrecognize that the same principles are equally applicable to, and can beimplemented in, all types of semiconductor processing, and that any suchvariations do not depart from the true spirit and scope of the presentinvention. Moreover, in the following detailed description, referencesare made to the accompanying figures, which illustrate specificembodiments. Electrical, mechanical, logical and structural chances maybe made to the embodiments without departing from the spirit and scopeof the present invention. The following detailed description is,therefore, not to be taken in a limiting sense and the scope of thepresent invention is defined by the appended claims and theirequivalents.

Embodiments relate generally to methods and apparatus for a minimumvoltage-capacitance coefficient polysilicon-to-polysilicon(“polysilicon”) capacitor with performance characteristics comparable toor better than metal capacitors. More particularly, a first layer ofpolysilicon is deposited on a substrate such as silicon. The first layerof polysilicon is implanted with a high concentration of dopants such as7.5×10¹⁵ cm⁻² or higher as compared to normal polysilicon applications.A dielectric layer such as SiN is then deposited over the first layer ofdoped polysilicon using LPCVD techniques. A second layer of polysiliconcan be subsequently deposited over the dielectric layer. The secondlayer of polysilicon is doped with an equivalent concentration ofdopants as the first layer of polysilicon. The high implant dosing andequivalent doping of the first and second layers of polysilicon providea voltage capacitance coefficient (VCC) over a selected voltage rangecomparable to or better than metal capacitors due to the low dispersionof the electrodes. Accordingly, the low VCC allows for integration ofthe equivalently doped polysilicon capacitors into linear applications.

FIGS. 1A-E collectively illustrate a process 100 for forming anembodiment of the low VCC polysilicon capacitor. It should be readilyapparent to those of ordinary skill in the art that the process 100depicted in FIG. 1 represents a generalized schematic illustration andthat other steps may be added or existing steps may be removed ormodified.

As shown in FIG. 1A, process 100 may begin with a substrate 105. Thesubstrate 105 can be a silicon based material such as silicon dioxide(“SiO₂”) to form a low VCC polysilicon capacitor. The substrate 105 maybe prepared for formation of semiconductor devices in accordance withsemiconductor processes such as CMOS, BICMOS, MOSFET or othersemiconductor technologies as known to those skilled in the art.

Referring to FIG. 1B, a first layer of polysilicon 110 can be depositedon the substrate 105. The polysilicon 110 can be a material comprisingmultiple small silicon crystals deposited on a substrate using chemicalvapor deposition techniques as known to those skilled in the art. Insome embodiments, the polysilicon 110 can also be implemented withamorphous silicon. The polysilicon 110 layer can be deposited to apredetermined thickness. In some embodiments, the thickness can rangefrom about 2000 to 2700 Angstroms.

After the deposition process, the polysilicon can be implanted withimplants species such as n-type dopants such as phosphorus, arsenic, etcor p-type dopants such as boron, gallium, etc. For various embodiments,the dopant concentration for the first layer of polysilicon 110 canrange from about 6.1×10¹⁵ cm⁻² to about 1.2×10¹⁶ cm⁻², at an energylevel between 30 and 45 keV. In other embodiments, the dopantconcentration can be above or below the above-mentioned range dependingon the performance requirements of the selected polysilicon capacitor.Similarly, the thickness of the first layer of polysilicon can bedependent on the application of the eventual formed polysiliconcapacitor. In one embodiment, the thickness of the first layer ofpolysilicon is about 2000 Angstroms.

Referring to FIG. 1C, a dielectric layer 115 can be deposited over thefirst layer of polysilicon 110. The dielectric layer 115 can be amaterial that is highly resistant to electric current such as siliconnitride (“SiN”), SiO₂, Al₂O₃, Ta₂O₅, HfO₂, HFSiON, etc. In someembodiments, the thickness of the dielectric layer 115 can be about 350angstroms. It should be readily obvious to one skilled in the art thatthe thickness of the dielectric layer 115 is dependent on the desiredperformance characteristics of the eventual formed polysiliconcapacitor.

With reference to FIG. 1D, a second layer of polysilicon 120 can bedeposited over the dielectric layer 115. The second layer of polysilicon120 can be deposited using LPCVD techniques at a temperature of 620Celsius (C) for polysilicon or 530° C. for amorphous silicon to athickness of about 2000 Angstroms in some embodiments Subsequently, thesecond layer of polysilicon 120 can be implanted with an implant speciessuch as a n-type dopant at a concentration between 3.0×10¹⁵ atm/cm² and6×10¹⁵ atm/cm² at an energy level between 30 and 45 keV in someembodiments. As with the first layer of polysilicon 110, the dopantconcentration and thickness of the second layer of polysilicon arerelated to desired characteristics of the eventual formed capacitor.

Referring to FIG. 1E, the capacitor 125 may be annealed to activate theimplanted dopants in the first and second layers of polysilicon, 110,120, respectively. The range of temperatures for the annealing can rangefrom about 800 to 1000 degrees Celsius.

As a processing note, the selection of the dopant concentration for thesecond layer of polysilicon 120 can also be dependent on theconcentration of dopant for the first layer of polysilicon 110. Moreparticularly, the amount of dopant for the second layer of polysiliconcan be equivalent to the concentration of dopants in the first layer ofpolysilicon 110 such that the first and second layers of polysiliconhave equivalent concentrations of dopants. The high implant doses andthe equivalent doping provide for a high degree of voltage linearityperformance over a voltage range comparable to or better than the metalcapacitors which are described with respect to FIGS. 2, 3B.

FIG. 2 illustrates a graph of the voltage linearity of variouspolysilicon capacitors with the top plate doped at variousconcentrations compared to a conventional metal capacitor. FIG. 2 ispremised on several factors. One factor is that the thickness of thedielectrics for polysilicon capacitors (210-220) is 325 Angstroms andthe metal capacitor is 350 angstroms. The implant dose for the bottomplate of the polysilicon capacitors is 7.9×10¹⁵ atm/cm² as anotherfactor. Yet another premise is that the metal capacitor is formed withtwo TiN electrodes, which shows the lowest dispersion over the voltagerange.

As shown in FIG. 2, the voltage linearity graph of the metal capacitor205 shows a relatively flat curve between −10 V and 10 V. The voltagelinearity graph of a first capacitor 210 (doped at 1.6×10¹⁶ atm/cm² forthe top plate) shows a variation of substantially 0.00005 from thevoltage linearity graph of the metal capacitor 205 for the normalizedcapacitance over the voltage range −10 V to 10 V. Similarly, the voltagelinearity graph for a second capacitor 215 (doped at 9×10¹⁵ atm/cm² forthe top plate) shows a variation of substantially 0.0025 from thevoltage linearity graph of the metal graph of the metal capacitor 205for the normalized capacitance over the voltage range −10 V to 10V. Forthe third polysilicon capacitor 220 (doped at 3×10¹⁵ atm/cm² for the topplate), the variation from the metal capacitor 205 is greater (on theorder of 0.02) than the first and second polysilicon capacitors 210,215, respectively. However, the third polysilicon capacitor 220 can beacceptable depending on the performance requirements of the device.Thus, one aspect of the voltage linearity of the various devices in FIG.2 is that it tends to show that the higher doses of dopant generallyimprove the voltage linearity characteristics of the polysiliconcapacitors. Another aspect that is shown in FIG. 2 is the ability to“tune” or design the voltage linearity of the particular capacitor basedon the implant does. For example, if the performance requirement(s) ofthe capacitor is to operate between zero and five volts, a fabricatorcould select about 9×10¹⁵ atm/cm² or 7.5×10¹⁵ atm/cm² for the implantdose.

One observation of embodiments of the polysilicon capacitors is that thedopants in the polysilicon layers diffuse equally throughout theirrespective polysilicon layers. As a result, a polysilicon capacitorhaving a bottom plate thickness of 2700 Angstroms and dopantconcentration of 7.9×10¹⁵ atm/cm² can have an equivalent concentrationas a top plate thickness of 2000 angstroms and dopant concentration of6.0×10¹⁵ atm/cm². Moreover, it is further noted that by maintaining theratio of 7.9 to 6 for the bottom plate to top plate for increasingdopant concentrations, the voltage linearity of the polysiliconcapacitors can be improved as shown in FIGS. 3A-B.

FIG. 3A shows a plot 300 of VCC linear and VCC quad terms for variousconcentrations at the 7.9 to 6 ratio. The concentration of the dopantfor the top electrode ranges from 3e15 to 9e15 Atms/cm² from the leftside to the right side. The VCC linear and VCC quad terms arecoefficients for the curves representing the polysilicon capacitorsshown in FIG. 2.

As noted by the bottom bar 305 of the plot 300, the VCC linear and VCCquad terms generally show that the these terms are decreasing in valueas the equivalent dopant concentrations in both top and bottom plates ofthe polysilicon are increased. The last value of the bottom bar 305 inbox 310 represents the highest equivalent concentration having a VCClinear value of 21.32 and a VCC quad value of −17.23. Since thecoefficients are generally small and are in opposite sign, thisindicates that the last value is relatively flat over a given voltagerange. A plot of the VCC for the last concentration is shown in FIG. 3B.This particular capacitor was configured to have a dopant concentrationof 1.2×10¹⁶ cm⁻² in the bottom electrode and 9×10¹⁵ cm⁻² in the topelectrode. Both electrodes were also implemented with amorphous silicon.

FIG. 3B is a normalized capacitance versus voltage range graph 320 forthe same metal capacitor 205 shown in FIG. 2 and a polysilicon capacitor325 having VCC linear value of 21.32 and a VCC quad value of −17.23(shown in FIG. 3A). As shown in FIG. 3B, the variation of thepolysilicon capacitor 325 is substantially on the order of 0.0015 from−10V to 10 V, which can be comparable to the metal capacitor 205 overthe same range. Accordingly, high implant doses along with the implantdoses being equivalent for the top and bottom plate of the polysiliconcapacitor provide for VCC characteristics comparable to or better thanmetal capacitors.

It is to be understood that the terms “top”, “bottom”, “side”, “upper”,“lower”, “front”, “rear”, “horizontal”, “vertical” and the like are usedherein merely to describe points of reference and do not limit thepresent invention to any specific configuration or orientation.

Notwithstanding that the numerical ranges and parameters setting forththe broad scope of the invention are approximations, the numericalvalues set forth in the specific examples are reported as precisely aspossible. Any numerical value, however, inherently contains certainerrors necessarily resulting from the standard deviation found in theirrespective testing measurements. Moreover, all ranges disclosed hereinare to be understood to encompass any and all sub-ranges subsumedtherein. For example, a range of “less than 10” can include any and allsub-ranges between (and including) the minimum value of zero and themaximum value of 10, that is, any and all sub-ranges having a minimumvalue of equal to or greater than zero and a maximum value of equal toor less than 10, e.g., 1 to 5.

While the invention has been described with reference to the exemplaryembodiments thereof, those skilled in the art will be able to makevarious modifications to the described embodiments without departingfrom the true spirit and scope. The terms and descriptions used hereinare set forth by way of illustration only and are not meant aslimitations. In particular, although the method has been described byexamples, the steps of the method may be performed in a different orderthan illustrated or performed simultaneously. Those skilled in the artwill recognize that these and other variations are possible within thespirit and scope as defined in the following claims and theirequivalents.

1. A method of forming a capacitor, the method comprising: depositing afirst layer of polysilicon on a substrate; implanting a high dose ofdopant into the first layer of polysilicon; depositing a layer ofdielectric over the first layer of polysilicon; depositing a secondlayer of polysilicon over the layer of dielectric, and implanting anequivalent concentration of dopant as the first layer of polysiliconinto the second layer of polysilicon.
 2. The method of claim 1 furthercomprising annealing the capacitor.
 3. The method of claim 2, whereinthe annealing is done in a temperature range of between about 800 andabout 1000 Celsius.
 4. The method of claim 1, wherein the first layer ofpolysilicon has a thickness of between about 2000 to 2700 Angstroms,inclusively.
 5. The method of claim 1, wherein the layer of dielectrichas a thickness of substantially 350 Angstroms.
 6. The method of claim5, wherein the layer of dielectric comprises SiN.
 7. A capacitorcomprising: a first layer of polysilicon deposited over a substrate; adielectric layer deposited over the first layer of polysilicon; and asecond layer of polysilicon deposited over the dielectric layer, whereinthe first layer of polysilicon and the second layer of polysilicon areimplanted with dopant in substantially equivalent concentrations.
 8. Thecapacitor of claim 7, wherein a depth of the first layer of polysiliconis not equivalent to the depth of the second layer of polysilicon. 9.The capacitor of claim 8, wherein the first layer of polysilicon has athickness in the range of 2000 to 2700 Angstroms, inclusively.
 10. Thecapacitor of claim 7, wherein the layer of dielectric has a thickness ofabout 350 Angstroms.
 11. The capacitor of claim 9, wherein the layer ofdielectric comprises one of SiN, SiO₂, Al₂O₃, Ta₂O₅, HfO₂, HFSiON.
 12. Amethod for forming an integrated circuit in and on a silicon substratewith a polysilicon capacitor, the method comprising: depositing a firstlayer of polysilicon on a substrate; implanting a high dose of implantinto the first layer of polysilicon; depositing a layer of dielectricover the first polysilicon; depositing a second layer of polysiliconover the layer of dielectric, and implanting an equivalent concentrationof implant as the first layer of polysilicon into the second layer ofpolysilicon.
 13. The method of claim 12 further comprising annealing thepolysilicon capacitor.
 14. The method of claim 12, wherein the annealingthe polysilicon capacitor is at a temperature between about 800 andabout 1000 Celsius.
 15. The method of claim 12, wherein the first layerof polysilicon has a thickness of between about 2000 and about 2700Angstroms, inclusively.
 16. The method of claim 12, wherein the layer ofdielectric has a thickness of about 350 Angstroms.
 17. The method ofclaim 16, wherein the layer of dielectric comprises is one of SiN, SiO₂,Al₂O₃, Ta₂O₅, HfO₂, HFSiON.